For the foreseeable future, high-performance computing architectures will be based on SMP clusters. Current examples of such platforms include Sun Ultra HPC machines, Compaq AlphaServers with Quadrics switches, SGI Origins, and the IBM SP system with SMP nodes. Moreover, the Department of Energy's Accelerated Strategic Computing Initiative (ASCI) program relies on the success of computational clusters (e.g., Option White, a 512-node IBM SP-2 with 16-way SMP nodes). While methodologies for symmetric multiprocessors and message-passing primitives for clusters are well developed, performance concerns dictate the use of a hybrid solution. Our complexity model and programming methodology will be based hierarchically upon realistic model components for message-passing and for symmetric multiprocessor parallel architectures. The current deployment of teraflops and the future development of petaflops systems will certainly require the exploitation of similar performance engineering models.
The future of high-performance computing relies on the efficient and scalable use of clusters with symmetric multiprocessor (SMP) nodes and low-latency, high-bandwidth interconnection networks. Hardware benchmark results reveal awesome performance rates for each component; however, few applications on SMP clusters ever reach a fraction of these peak speeds. We claim that the two predominant models for designing algorithms for shared-memory and for message-passing systems that have been extended to SMP clusters actually hinder scalable, high-performance applications. In contrast, our approach, a hybrid, hierarchical methodology, is a much closer abstraction of the underlying machine and is ideally suited to SMP clusters.
Our goal is to validate and refine a core complexity model, efficient primitives and libraries, along with the programming environment and performance monitoring and analysis tools needed to support the effective use of SMP clusters. Our approach is based on a hybrid model that will enable sophisticated users (computational scientists) to take full advantage of a system by using an iterative approach for refining a high-performance algorithm to discover its optimal implementation. Initially, we will focus on the development and prototyping of the complexity model and primitives and initiate work on the development of measurement tools. We will also show how to design, implement, analyze, and refine algorithms that take advantage of the hybrid programming model and contribute to significant speed-ups for real computational science problems. These will include some basic combinatorial support tasks (e.g., searching, sorting, and basic graph and multidimensional geometric algorithms) and selected numerical computations (e.g., fast transforms). Our goal of supporting high-performance applications will be driven through the use of real codes for combinatorics, landscape ecology, remotely-sensed image processing, multi-phase fluid flow, and particle physics simulation applications.
Our project is based on and will benefit from a large number of ongoing activities and funded projects at the University of New Mexico. The High Performance Computing, Education and Research Center (HPCERC), affiliated with the NSF Partnerships for Advanced Computational Infrastructure NCSA, provides an umbrella for high-performance computing research activities on campus. HPCERC has on-going research activities in algorithms; computational mechanics, physics, and chemistry; image processing; and visualization. HPCERC operates and manages several high-performance computing platforms accessible and applicable to our project: the new NSF PACI Alliance / University of New Mexico Roadrunner Linux SuperCluster (64 dual-Pentium II processors, interconnected by Myrinet) and a large SP with SMP nodes at the Maui High Performance Computing Center. The Department of Computer Science, under an NSF Infrastructure grant, has set up a cluster of workstations connected with Myrinet. These clusters will serve as the main platforms for our effort; they can be linked to each other through ATM switches and the campus network.